The invention relates to a method and a device in particular for data exchange between memory and logic modules.
The transfer rate of (memory) information from a memory module to a processor, and vice versa, is currently a main factor for the limitation in the performance of computers. While modern processors achieve frequencies of 800 MHz and corresponding transfer rates, the frequencies for the data exchange between processor/controller and memory are, for technical reasons, currently 100 to at most 133 MHz. Therefore, new circuits and/or methods are urgently being sought in order to diminish the significance of this limiting factor and to utilize the high processor frequencies in the application as well.
Previous methods for increasing the transfer rate are essentially based on two principles:
(A) First, increases of the data transfer are sought through parallelism: that means a higher number of pins of the interface between the modules. The data transfer rate behaves linearly with respect to the number of pins.
(B) Second, increases are sought by increasing the clock frequency during the transfer, either by increasing the clock frequency in the processor and in the memory module or by utilizing the leading and trailing edges of the signal for transferring a respective information unit.
The former again leads to a transfer rate that rises linearly with frequency; the latter leads to an increase by the factor 2. In this case, the xe2x80x9crealxe2x80x9d frequency on the data pins in the case of continually changing data is also twice as high.
The first above-outlined concept is used, for example, in memory DIMMs and can only be implemented in a limited fashion owing to the high space requirement of many lines, e.g. on a motherboard of a computer, and on account of the number of interface pins which is limited by the IC size. Moreover, the costs for the motherboards and/or the IC packages greatly increase when there are many lines. The mutual influencing of the signals greatly increases and the transfer reliability thus decreases. If a plurality of memory modules are used in parallel on a module in order that the number of pins of an individual module is kept low, then the minimum memory size of the module greatly increases: e.g. nine 256 MBit modules each having eight data lines yield a bus width of 72 bits but constitute a minimum memory amount (xe2x80x9cgranularityxe2x80x9d) of 256 Mbytes (with error correction). This is unnecessary and too expensive for many low-cost applications.
The second above-outlined concept is utilized, for example, in direct Rambus DRAMs, double data rate SDRAMs, and allows a lower number of pins and thus theoretically a lower granularity. In return, however, there is a radical increase in the requirements imposed on the temporal accuracy of all the modules involved. In particular, the data transfer is difficult via a relatively long bus system (tens of centimeters) with low-quality printed signal lines. In the case of direct Rambus, the requirements imposed on the timing accuracy of the memory modules therefore have to be radically raised, which makes the production and testing of these modules difficult and expensive and reduces the yield.
It is accordingly an object of the invention to provide a method and a device for data exchange in particular between memory and logic modules, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which makes possible further increases in the data transfer rate without resulting in the problems outlined above.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for data exchange, particularly between memory modules and logic modules, which comprises:
converting, at a transmitter end, a given multidigit digital signal into a corresponding analog signal;
transmitting the analog signal to a receiver end; and
converting, at the receiver end, the analog signal into a multidigit digital signal identical to the given multidigit digital signal of the transmitter end.
In accordance with an added feature of the invention, a plurality of received analog signals are stored at the receiver end and the analog signals are processed using time division multiplexing.
In accordance with an additional feature of the invention, at the receiver end, the digital signal converted from the received analog signal is calibrated with regard to at least one signal value. Preferably, this is the maximum signal value.
In accordance with another feature of the invention, influences of attenuation between the transmitter end and the receiver end are eliminated by the calibration at the receiver end. In a preferred mode, the calibration at the receiver end utilizes a linearity of the analog signal fed into the receiver end.
With the above and other features in view there is provided, in accordance with the invention, a device for data exchange between a transmitter and a receiver, such as a memory module and a logic module. The device comprises:
a digital/analog converter at the transmitter, the digital/analog converter converting a plurality of bit positions of a multidigit digital signal into a corresponding analog signal;
a transfer link configured to transmit the analog signal to the receiver; and
an analog/digital converter at the receiver end, the analog/digital converter converting the analog signal back into a multidigit digital signal identical to the multidigit digital signal at the transmitter.
In accordance with again an added feature of the invention, the analog/digital converter includes a capacitor for briefly storing a respective voltage state of the received analog signal, and the capacitor is subsequently discharged via a constant-current source; and a concurrent counter is configured to decode the signal by measuring a time required for the capacitor to be discharged.
In accordance with again an additional feature of the invention, the analog/digital converter operates according to the principle of successive approximation and has an internal D/A converter, whose analog output value is compared by a comparator with the received analog signal to be decoded and is adjusted until a resulting analog signal and the analog signal transmitted by the transmitter have the same magnitude.
In accordance with again another feature of the invention, the internal D/A converter of the analog/digital converter has a calibration device configured to calibrate the digital signal, generated for the comparison, for at least one value of the analog input signal.
In accordance with a concomitant feature of the invention, the calibration device in the D/A converter of the successive approximation analog/digital converter has a plurality of transistors and an additional overdrive transistor having a saturation current exactly half of a saturation current of a transistor corresponding to a least significant bit position of the converted digital signal, and means for adjusting, in dependence on a magnitude of a calibration signal transmitted by the transmitter, respective currents flowing through the transistors of the D/A converter of the successive approximation analog/digital converter in fine steps until the analog signal received as calibration signal and the comparison calibration signal generated by the D/A converter of the successive approximation analog/digital converter are virtually identical.
In a general form, in the method according to the invention, a D/A converter is required at the respective transmitter end, which converts a plurality of bits (digital states) for the transfer via a transfer link (bus system) into an analog state (a current or a voltage). This conversion has to be reversed at the receiver end, with the result that the digital signal obtained from the received analog signal by analog/digital conversion at the receiver end is identical to the transmitted digital signal.
Digital/analog converters which are suitable for the abovementioned purpose are known. Likewise, there are simple analog/digital converters, e.g. those which operate according to the following principles: the storage of a voltage state in a capacitor and subsequent discharge of the capacitor via a constant-current source, the decoding being effected by a concurrent counter which measures the time required for the discharge, or a successive approximation: in this case, at the receiver end, a D/A converter is used in the A/D converter and its analog output value is compared with the analog signal to be decoded and is adjusted until the resulting signal and the signal received from the transmitter have the same magnitude. This principle of the successive approximation A/D converter has the advantage that it can be calibrated relatively easily.
For the above procedure (A), the method presented here and the device can reduce the number of required pins by a factor k (integer) which corresponds to the number of bits of the digital signal which are encoded into an analog state. In the case (B), for the same operating frequency, the signal transfer rate can be increased by the factor k or, given a constant transfer rate, the frequency can be reduced by the factor k.
With an increased bandwidth, the method according to the invention allows a plurality of modules to use the same bus line, as previously in the case of SDRAM, EDORAMs, direct Rambus, in that all modules not read at a point in time switch their outputs to xe2x80x9chigh impedancexe2x80x9d. The level of the bus line is then determined solely by the level driven by the active module. In other words, the system is compatible with existing bus systems.
Since the decoding of an analog value at the receiver end requires some time, it is advantageous to use a plurality of decoders, i.e. A/D converters, per pin on a chip and to time division multiplex the input signals between them. This would enable a further increase in the bandwidth as long as the physical properties of the bus system do not entail a limitation thereof. To that end, the analog input signal has to be briefly buffer-stored, e.g. in capacitors.
In a development, a successive approximation analog/digital converter to be used at the receiver end has a calibration device which carries out a simple calibration on the basis of at least one input signal while at the same time avoiding a discretization error.
It goes without saying that the method according to the invention and the device designed for implementing it are not restricted to data transfer between memory and logic modules, but rather can advantageously be used wherever considerable limitations of the transfer rate could previously be observed in the transfer of digital data.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a Method and device for data exchange between memory and logic modules, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.